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Ordering number : EN4079B
CMOS LSI
LC8901, 8901Q
Digital Audio Interface Receiver
Overview
The LC8901 and LC8901Q are LSIs for use in IEC958, EIAJ CP-1201 format data transmission between digital audio equipment. These LSIs are used on the receiving side, and handle synchronization with the input signal and demodulation of that signal to a normal format signal.
Package Dimensions
unit: mm 3025B-DIP42S
[LC8901]
Features
* On-chip PLL circuit synchronizes with the transmitted IEC958, EIAJ CP-1201 format signal. * Provides 20-bit LSB first and 16-bit MSB first audio data output functions. * Microprocessor interface for mode settings and code output * System clock can be selected to be either 384fs or 512fs. * Provides both a digital source mode and an analog source mode. * Fabricated in a Si-gate CMOS process. * 5 V single-voltage power supply unit: mm 3148-QIP44M
[LC8901Q]
SANYO: DIP42S
SANYO: QIP44M
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D3095HA (OT)/52593JN/7202JN No. 4079-1/15
LC8901, 8901Q Usage overview diagram Assumes the use of both digital and analog source modes. Digital source mode
Analog source mode
Pin Assignment
LC8901 (DIP42S)
LC8901Q (QIP44M)
No. 4079-2/15
LC8901, 8901Q Block Diagram
No. 4079-3/15
LC8901, 8901Q Pin Functions LC8901 (DIP42S)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol DIN1 DIN2 DIN3 DIN4 DGND DIN5 DIN6 DOUT1 DOUT2 RC1 RC2 LPF STOP TEST1 TEST2 AVDD R AGND VIN VCO DGND CLK XSYS XIN1 XIN2 DVDD LOCK ERROR FS256 CLKOUT EMPHA BCLK DATAOUT LRCK SUB1 SUB2 DO DI CE CL XMODE DVDD I/O I I I I -- I I O O I O I I I I -- I -- I O -- I I I O -- O O O O O O O O O O O I I I I -- Digital system ground Data input pins without built-in amplifiers Data input pins with built-in amplifiers Pin function and circuit operation
Input data through output
RC oscillator connection High: LPF time constant switching mode, low: fixed mode. This pin is normally high. High: VCO operation stopped, low: normal operation Test pins (These pins are normally low.) Analog system power supply VCO oscillator band adjustment Analog system ground VCO free-running oscillator setup PLL low-pass filter Digital system ground Clock mode switching. High: 512fs, low: 384fs Crystal mode setting. High: crystal mode Crystal oscillator connection Digital system power supply High: PLL locked, low: unlocked Error mute signal output 256fs clock output VCO oscillator and crystal oscillator clock output High: emphasis present, low: no emphasis Bit clock output Audio data output Left/right clock output. High: left channel, low: right channel Sampling frequency output Microprocessor interface output Microprocessor interface input Microprocessor interface chip enable input Microprocessor interface clock input Used to start system operation after power on. Digital system power supply
Note: The DIP42S package version has one fewer each of the digital system power supply and digital system ground pins than the QIP44M package version.
No. 4079-4/15
LC8901, 8901Q LC8901Q (QIP44M)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol DIN5 DIN6 DOUT1 DOUT2 RC1 RC2 LPF STOP TEST1 TEST2 DVDD AVDD R AGND VIN VCO DGND CLK XSYS XIN1 XIN2 DVDD LOCK ERROR FS256 CLKOUT EMPHA DGND BCLK DATAOUT LRCK SUB1 SUB2 DO DI CE CL XMODE DVDD DIN1 DIN2 DIN3 DIN4 DGND I/O I I O O I O I I I I -- -- I -- I O -- I I I O -- O O O O O -- O O O O O O I I I I -- I I I I -- Digital system ground Data input pins with built-in amplifiers Data input pins without built-in amplifiers Pin function and circuit operation
Input data through output
RC oscillator connection High: LPF time constant switching mode, low: fixed mode. This pin is normally high. High: VCO operation stopped, Low: normal operation Test pins (These pins are normally low.) Digital system power supply Analog system power supply VCO oscillator band adjustment Analog system ground VCO free-running oscillator setup PLL low-pass filter Digital system ground Clock mode switching. High: 512fs, low: 384fs Crystal mode setting. High: crystal mode Crystal oscillator connection Digital system ground High: PLL locked, low: unlocked Error mute signal output 256fs clock output VCO oscillator and crystal oscillator clock output High: emphasis present, low: no emphasis Digital system ground Bit clock output Audio data output Left/right clock output. High: left channel, low: right channel Sampling frequency output Microprocessor interface output Microprocessor interface input Microprocessor interface chip enable input Microprocessor interface clock input Used to start system operation after power on. Digital system power supply
No. 4079-5/15
LC8901, 8901Q
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -30 to +75 -55 to +125 Unit V V V C C
Allowable Operating Ranges
Parameter Supply voltage Operating temperature Symbol VDD Topr Conditions min 4.5 -30 typ 5.0 max 5.5 +75 Unit V C
DC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V
Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Current drain Input amplitude Note: 1. 2. 3. 4. Symbol VIH VIL VIH VIL VOH VOL IDD VIN *1 *1 *2 *2 IOH = -1 A IOL = +1 A *3 *4 10 0.4 20 Conditions min 2.2 -0.3 0.8 VDD -0.3 VDD - 0.05 VSS + 0.05 30 VDD + 0.3 typ max VDD + 0.3 0.8 VDD + 0.3 0.2 VDD Unit V V V V V V mA Vp-p
Input pins other than the data input pins DIN1, DIN2, DIN3, and DIN4, and the XMODE pin XMODE pin When VDD = 5.0 V, Ta = 25C, and the input data FS is 48 kHz At the conditions prior to the input capacitance of the data input pins DIN1, DIN2, DIN3, and DIN4
AC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V
Parameter Output pulse width Output setup time Output data hold time Output delay for high Output delay for low Symbol tWBO tDSO tDHO tbdH tbdL fs = 48 kHz Conditions min 160 80 80 -10 -10 0 0 10 10 typ max Unit ns ns ns ns ns
Note: Load capacitance: Each pin has a load capacitance of 30 pF.
No. 4079-6/15
LC8901, 8901Q Waveforms for the AC Characteristics
Microprocessor Interface Block AC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V
Parameter CL low-level pulse width CL high-level pulse Width Data setup time Data hold time CL rise time CL fall time CE delay time CL delay time Data delay time CL and data delay time CL delay time CL and CE delay time Symbol TWL TWH TDS TDH Tr Tf TD1 TD2 TD3 TD4 TD5 TD6 With a 30 pF load With a 30 pF load 100 1.0 CL, CE, DI CL, CE, DI 1.0 50 25 50 Conditions min 100 100 50 50 30 30 typ max Unit ns ns ns ns ns ns s ns ns ns ns s
No. 4079-7/15
LC8901, 8901Q Waveforms for the Microprocessor Interface Block Input mode
Output mode
Clock Modes The LC8901 and LC8901Q support 4 clock modes selected by the XSYS and CLK pins.
XSYS pin L L H H CLK pin L H L H Mode The system clock is 384fs. It is synchronized to the input data, which is then demodulated. The system clock is 512fs. It is synchronized to the input data, which is then demodulated. The system clock is 384fs, but data is neither synchronized nor demodulated. The 256fs, BCLK, and LRCK signals are output based on the crystal oscillator. The system clock is 512fs, but data is neither synchronized nor demodulated. The 256fs, BCLK, and LRCK signals are output based on the crystal oscillator.
1. 2. 3. 4.
When the CLK pin is low, the 256fs clock duty is H:L = 2:1. When the CLK pin is high, the duty is 1:1. Modes in which XSYS is high assume the analog source mode from the usage overview diagram. The LSI automatically switches to analog source mode if there is no signal applied to the data demodulation input pin. 5. The STOP pin controls stopping the VCO. In analog source mode, the system will not stop if the STOP pin is set high. However, setting this pin high in digital source mode while the PLL circuit is operating will stop the system.
No. 4079-8/15
LC8901, 8901Q LPF Pin Setting the LPF pin high sets the PLL low-pass filter time constant to a mode in which it is automatically switched by the PLL locking state. This pin should be set high normally. Microprocessor Interface The data input pin setting, output data format setting, and subcode output are controlled through the microprocessor interface. The following item describes the interface I/O formats. Microprocessor Interface Format
Address Bits B0 to A3 in the format figure are the address. There are two dedicated addresses allocated, one for data input and one for data output. Use the input address for data input and the output address for data output. Address Codes
Mode Data input Data output B0 H L B1 L H B2 H H B3 L L A0 L L A1 H H A2 H H A3 L L
No. 4079-9/15
LC8901, 8901Q Microprocessor Interface Input 1. Input pin setting The data input pins DIN1 to DIN4 have built-in amplifiers and can receive signals from a minimum amplitude of 400 mVp-p to a maximum amplitude of VDD plus 0.3 V. Pins DIN5 and DIN6 do not have built-in amplifiers and are only for use with optical inputs. Amplifiers must be inserted before the inputs if these pins are to be used with coaxial input.
The data input system multiplexer is controlled by input from the microprocessor interface. The tables show the relationship between the microprocessor interface I5 to I13 codes and the data demodulation, DOUT1, and DOUT2 signals. Bits I0 to I4 and I15 are ignored.
I5 I6 I7 Data demodulation input I8 I9 I10 DOUT1 I11 I12 I13 DOUT2 L L L DIN1 H L L DIN2 L H L DIN3 H H L DIN4 L L H DIN5 H L H DIN6 L H H GND H H H GND
L L L DIN1 L L L DIN1
H L L DIN2 H L L DIN2
L H L DIN3 L H L DIN3
H H L DIN4 H H L DIN4
L L H DIN5 L L H DIN5
H L H DIN6 H L H DIN6
L H H GND L H H GND
H H H GND H H H GND
2. Audio data output mode setting There are two audio data output modes, one with a 16-bit MSB first format and one with a 20-bit LSB first format. The I14 code determines the setting.
I14 Audio data output mode L 16-bit MSB first format H 20-bit LSB first format
No. 4079-10/15
LC8901, 8901Q Microprocessor Interface Output The table lists the content of the bits D0 to D15 in the microprocessor interface format.
Bit D0 D1 D2 D3 D4 D5 to D12 D13 D15 Invalid bit. A low level is always output. Indicate the sampling frequency. Correspond to the 2 external output port pins. Indicates the copy flag. Low: copy protected, high: copying allowed. Outputs the first bit in the channel status bits. These bits serially output the 8 bits of the channel status category code. Invalid bit. A low level is always output. Meaning
Interpretation of Bits D1 and D2
Sampling frequency D1 D2 32 kHz H H 44.1 kHz L L 48 kHz L H #1 H L
1. The #1 state is the state in which the data was cleared by a PLL lock error. 2. The initial settings of the modes immediately after the XMODE pin is switched from low to high are all low level. However, D1 and D2 will indicate the #1 state. 3. The microprocessor data output registers are all cleared to 0 when PLL locking is lost. However, D1 and D2 will indicate the #1 state. 4. The interval between two microprocessor data readout operations must be at least 6 ms. Also, when PLL locking is lost the microprocessor must wait at least 6 ms after the error signal goes low before accessing data. FS Code The SUB1 and SUB2 pins indicate the input data sampling frequency.
Sampling frequency SUB1 SUB2 32 kHz H H 44.1 kHz L L 48 kHz L H #1 H L
The #1 state is the state in which the data was cleared by a PLL lock error. Lock and Errors 1. LOCK pin: This pin goes high when preamble detection has succeeded for 2 consecutive frames and thus indicates the PLL locked state. This pin is low at all other times. In particular, it is low when the XMODE pin is low, when the STOP pin is high, and in analog source mode. 2. ERROR pin: Goes high when an error exists in the input data or when the PLL circuit is in the unlocked state. When the data returns to normal it holds the high level for about 200 to 300 ms and then falls to low. This period is inversely proportional to the input data sampling frequency. This pin is high when the XMODE pin is low, when the STOP pin is high, and in analog source mode. 3. Data processing when errors occur: The table below lists the data processing that is performed when an error occurs.
Error type Continuous parity errors for up to 8 cycles Continuous parity errors for 9 or more cycles PLL lock error Audio output data The previous data value is output All zero data is output All zero data is output Held Held Data is cleared and the #1 state is indicated. C bit output data
Note: The term "C bit data" means data that was decoded from the channel status bit. * When there is no data input to the data demodulation system, the system automatically switches from PLL operation to the crystal oscillator and enters analog source mode. * These pins indicate a state identical to a PLL lock error in any of the following cases: The STOP pin is high, the XMODE pin is low, or the system is in analog source mode.
No. 4079-11/15
LC8901, 8901Q PLL 1. The VCO is formed from a ring oscillator. 2. PLL operation starts when correct data is input to the data demodulation system and the XMODE pin goes high. 3. The low-pass filter time constant can be automatically switched according to the PLL lock state by setting the LPF pin high. 4. To prevent PLL locking failures, if a PLL locking operation is started and the PLL does not lock within a fixed period, reinitialize the PLL system, and start the PLL locking operation again. 5. PLL operation is forcibly stopped by setting the STOP pin high. Normal operation will start again if the pin is set low. XMODE Pin The XMODE pin resets the system. Normal system operation is started by setting this pin high after the power supply voltage has risen to at least 4.5 V. If the XMODE pin is set low, the VCO free-running clock is output from the FS384 pin and the internal circuits are reset. Power-on Sequence Diagram
1. No input pins should be accessed until the XMODE pin has gone high and the system has started to operate. 2. The microprocessor interface pins must not be accessed until the XMODE pin has gone high and the system has started to operate. 3. The data output pins must not be accessed until the ERROR pin has gone low after the XMODE pin has gone high.
No. 4079-12/15
LC8901, 8901Q Data Output Timing The figure below shows the data output timing. 1. Data is output in synchronization with the falling edge of the BCLK signal. 2. Data, BCLK, and LRCK are output in synchronization with the rising edge of the 256fs clock. Timing Chart
No. 4079-13/15
LC8901, 8901Q Sample Application Circuit
Note: All input pin resistors and capacitors are the same.
Recommended Constants for the Application Circuit
Item Symbol R1 R2 R3 R4 Resistors R5 R6 R7 R8 R9 C1 C2 Capacitors C3 C4 C5 Constant value 330 k* 33 k 24 k 5.1 k 5.1 k 150 180 k 200 k 10 k 0.1 F* 1000 pF 0.01 F 10 pF to 47 pF 10 F to 100 F
Note: * The constants listed above are for applications that connect to the input pins using coaxial cable. If connection is through an optical receiver module, remove the C1 capacitors and use 56 k resistors for R1. Note that DIN5 and DIN6 are only for use with optical receiver modules.
No. 4079-14/15
LC8901, 8901Q Sample Optical Receiver Module Circuit
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 4079-15/15

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